1. Technical Field
This invention relates in general to keypad arrays and more particularly, to the reduction of input/outputs of such arrays.
2. Description of the Related Art
Many electronic devices include keypads for permitting users to enter alphanumeric symbols into the device. For example, almost all mobile communications units include a keypad having a plurality of keys in which the user of the mobile unit can dial numbers or enter text through selective pressing of the keys. The keys in a typical keypad are positioned such that they form an array having a number of columns and rows. As an example, many keypads have three columns and four rows, and this particular configuration is commonly referred to as a 3×4 array. Other designs are possible, such as 3×5, 4×5 and 6×5 arrays.
The devices that include these keypads have some type of processor to receive and process signals from the keys. In response to the receipt of these signals, the processor will perform some function or operation, which reflects the user's sequence of pressing the keys. Currently, in interrupt-driven systems, the processor has an input/output (I/O) for each of the columns and rows that make up the keypad array of the device. For example, in a 3×4 array, the processor will have an I/O for each of the columns (three of them) and each of the rows (four of them) for a total of seven I/Os. This one-to-one correspondence is inefficient and consumes a significant amount of processor I/Os, particularly if the number of keys in an array increases. As an example, the implementation of a 4×10 array, which contains 40 keys, requires fourteen processor I/Os. This inefficient consumption of processor I/Os is likely to continue in the future due to the expansion of the number of keys on electronic devices. Thus, what is needed is a method and system for reducing the number of I/Os for a particular keypad array.